Ciena is a global leader in high-speed connectivity, focusing on a people-first approach. The Digital Verification Engineer will implement innovative verification strategies to simulate and validate functional blocks and subsystems for the Wavelogic family of products in the telecommunications industry.
Responsibilities
- Read and understand the functional requirements specification document(s) and communicate and collaborate with systems engineers and architects
- Responsible for the complete and thorough validation of one or more functional blocks by using an appropriate combination of simulation, formal and coverage methods
- Create the verification, functional coverage and formal verification test plans
- Part of a team that is accountable for the creation of testbench environment and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable
- Perform coverage driven verification, monitor regressions and debug resulting failures with the help of the function's designer
- Report on status updates on a regular basis
Skills
- Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc or MEng/MSc level
- A highly motivated self-starter, able to work independently, while being a team player
- Ability to methodically solve complex technical problems
- Excellent organization, written and oral (English) communication skills
- Proficiency above the intermediate level with the use of System Verilog, SVA, and simulators from major vendors
- Proven ability in determining appropriate and comprehensive digital verification and coverage strategies
Benefits
- Medical, dental, and vision plans
- Participation in 401(K) (USA) & DCPP (Canada) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company-paid holidays
- Paid sick leave
- Vacation time
- Paid Family Leave and other leaves of absence
Company Overview
Company H1B Sponsorship
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